Know about our research

A software design comprises different diagrams which describe the system at different levels of abstraction. Students face difficulties in making sense of a given software design, and evaluating it against the given requirements.

A key finding from our research is that students focus on superficial aspects of a design, and do not focus on key elements of the design such as how various methods are called (control flow), and how data variables change on the basis of these method calls (data flow). Hence, we have designed the VeriSIM pedagogy which scaffolds students to create effective models of a given design by simulating the control flow and data flow of various scenarios in the design.

The team has implemented the pedagogy in the form of a learning environment called VeriSIM.

• Disciplinary Practice: Software Design Evaluation

• Topic: Software Design

• Target audience: Third-Final Year CS/IT undergraduates

• No of students trained: 120

• Explore VeriSIM

• Research Team: Prajish Prasad, Sridhar Iyer

Publications:

1. Prasad, P., & Iyer, S. (2020, August). How do Graduating Students Evaluate Software Design Diagrams?. In Proceedings of the 2020 ACM Conference on International Computing Education Research (pp. 282-290). [ Paper | Presentation Video ]
   

2. Prasad, P., & Iyer, S. (2020, June). VeriSIM: a learning environment for comprehending class and sequence diagrams using design tracing. In Proceedings of the ACM/IEEE 42nd International Conference on Software Engineering: Software Engineering Education and Training (pp. 23-33). [ Paper | Blog Post | Presentation Video ]
   

3. Prasad, P., & Iyer, S. (2020, November). Inferring Students’ Tracing Behaviors from Interaction Logs of a Learning Environment for Software Design Comprehension. In Koli Calling'20: Proceedings of the 20th Koli Calling International Conference on Computing Education Research (pp. 1-2). [ Paper| Poster ]